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ISCAS
2007
IEEE
141views Hardware» more  ISCAS 2007»
14 years 2 months ago
Towards a GBit/s Programmable Decoder for LDPC Convolutional Codes
Abstract— We analyze the decoding algorithm for regular timeinvariant LDPC convolutional codes as a 3D signal processing scheme and derive several parallelization concepts, which...
Emil Matús, Marcos B. S. Tavares, Marcel Bi...
ASPDAC
2006
ACM
122views Hardware» more  ASPDAC 2006»
14 years 2 months ago
Reusable component IP design using refinement-based design environment
- We propose a method of enhancing the reusability of the component IPs by separating communication and computation for a system function. In this approach, we assume that the comp...
Sanggyu Park, Sang-yong Yoon, Soo-Ik Chae
FCCM
2005
IEEE
124views VLSI» more  FCCM 2005»
14 years 2 months ago
Parallel Hardware Implementation of Cellular Learning Automata Based Evolutionary Computing (CLA-EC) on FPGA
The CLA-EC is a model obtained by combining the concepts of cellular learning automata and evolutionary algorithms. The parallel structure of the CLA-EC makes it suitable for hard...
Arash Hariri, Reza Rastegar, Morteza Saheb Zamani,...
HOTI
2005
IEEE
14 years 2 months ago
A Scalable, Self-Routed, Terabit Capacity, Photonic Interconnection Network
We present SPINet (Scalable Photonic Integrated Network), an optical switching architecture particularly designed for photonic integration. The performance of SPINet-based network...
Assaf Shacham, Benjamin G. Lee, Keren Bergman
ICCSA
2004
Springer
14 years 1 months ago
Publishing and Executing Parallel Legacy Code Using an OGSI Grid Service
Abstract. This paper describes an architecture for publishing and executing parallel legacy code using an OGSI Grid service. A framework is presented that aids existing legacy appl...
Thierry Delaitre, Ariel Goyeneche, Tamás Ki...