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» NoC Power Estimation at the RTL Abstraction Level
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LCTRTS
2010
Springer
14 years 2 months ago
Design exploration and automatic generation of MPSoC platform TLMs from Kahn Process Network applications
With increasingly more complex Multi-Processor Systems on Chip (MPSoC) and shortening time-to- market projections, Transaction Level Modeling and Platform Aware Design are seen as...
Ines Viskic, Lochi Lo Chi Yu Lo, Daniel Gajski
ESTIMEDIA
2007
Springer
14 years 1 months ago
Signature-based Microprocessor Power Modeling for Rapid System-level Design Space Exploration
This paper presents a technique for high-level power estimation of microprocessors. The technique, which is based on abstract execution profiles called ’event signatures’, op...
Peter van Stralen, Andy D. Pimentel
DGCI
2009
Springer
13 years 8 months ago
Grey Level Estimation for Discrete Tomography
Abstract. Discrete tomography is a powerful approach for reconstructing images that contain only a few grey levels from their projections. Most theory and reconstruction algorithms...
Kees Joost Batenburg, W. van Aarle, Jan Sijbers
DAC
2007
ACM
14 years 8 months ago
Shared Resource Access Attributes for High-Level Contention Models
Emerging single-chip heterogeneous multiprocessors feature hundreds of design elements contending for shared resources, making it difficult to isolate performance impacts of indiv...
Alex Bobrek, JoAnn M. Paul, Donald E. Thomas
ICCD
2005
IEEE
176views Hardware» more  ICCD 2005»
14 years 4 months ago
A Formal Framework for Modeling and Analysis of System-Level Dynamic Power Management
Recent advances in Dynamic Power Management (DPM) techniques have resulted in designs that support a rich set of power management options, both at the hardware and software levels...
Shrirang M. Yardi, Karthik Channakeshava, Michael ...