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» Noise considerations in circuit optimization
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VTS
1996
IEEE
112views Hardware» more  VTS 1996»
13 years 12 months ago
Optimal voltage testing for physically-based faults
In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus on two f...
Yuyun Liao, D. M. H. Walker
ISQED
2003
IEEE
109views Hardware» more  ISQED 2003»
14 years 1 months ago
Optimizing the Energy-Delay-Ringing Product in On-Chip CMOS Line Drivers
Abstract- This paper presents a detailed empirical study and analytical derivation of voltage wave-form and energy dissipation of global lines driven by CMOS drivers. It is shown t...
Soroush Abbaspour, Massoud Pedram, Payam Heydari
DATE
2009
IEEE
109views Hardware» more  DATE 2009»
14 years 2 months ago
A design methodology for fully reconfigurable Delta-Sigma data converters
This paper presents a design methodology for fully reconfigurable low-voltage Delta-Sigma converters as for instance used in next-generation wireless applications. The design metho...
Yi Ke, Jan Craninckx, Georges G. E. Gielen
ASYNC
2002
IEEE
124views Hardware» more  ASYNC 2002»
14 years 23 days ago
Synchronous Interlocked Pipelines
In a circuit environment that is becoming increasingly sensitive to dynamic power dissipation and noise, and where cycle time available for control decisions continues to decrease...
Hans M. Jacobson, Prabhakar Kudva, Pradip Bose, Pe...
ISQED
2008
IEEE
186views Hardware» more  ISQED 2008»
14 years 2 months ago
Reliability-Aware Optimization for DVS-Enabled Real-Time Embedded Systems
—Power and energy consumption has emerged as the premier and most constraining aspect in modern computational systems. Dynamic Voltage Scheduling (DVS) has been provably one of t...
Foad Dabiri, Navid Amini, Mahsan Rofouei, Majid Sa...