152 search results - page 29 / 31 » Noise considerations in circuit optimization |
FPL
2009
Springer
14 years 11 days ago
2009
Springer
We leverage properties of the logic synthesis netlist to define both a logic element architecture and an associated technology mapping algorithm that together provide improved lo...
TCAD
2010
13 years 2 months ago
2010
Abstract--This paper presents a technology mapping algorithm for field-programmable gate array architectures with dual supply voltages (Vdds) for power optimization. This is done w...
DAC
2011
ACM
12 years 7 months ago
2011
ACM
Existing thermal-aware 3D placement methods assume that the temperature of 3D ICs can be optimized by properly distributing the power dissipations, and ignoring the heat conductiv...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
The flip-chip package provides a high chip-density solution to the demand for more I/O pads of VLSI designs. In this paper, we present the first routing algorithm in the literatur...
ICCAD
2007
IEEE
14 years 4 months ago
2007
IEEE
— Energy efficiency has become one of the most important issues to be addressed in today’s System-on-a-Chip (SoC) designs. One way to lower the power consumption is to reduce ...