339 search results - page 26 / 68 » Noise-tolerant dynamic circuit design |
ETS
2009
IEEE
2009
IEEE
Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques
13 years 7 months ago
Due to the increased speed in modern designs, testing for delay faults has become an important issue in the postproduction test of manufactured chips. A high fault coverage is nee...
CAI
2004
Springer
13 years 9 months ago
2004
Springer
A complete hardware implementation of an evolvable combinational unit for FPGAs is presented. The proposed combinational unit consisting of a virtual reconfigurable circuit and evo...
SC
2005
ACM
14 years 3 months ago
2005
ACM
The interconnect plays a key role in both the cost and performance of large-scale HPC systems. The cost of future high-bandwidth electronic interconnects is expected to increase d...
GLVLSI
2010
IEEE
14 years 2 months ago
2010
IEEE
We present the architecture of a new Ordered Binary Decision Diagram library that is designed from the ground up to be space efficient. The main novelty lies in the library’s no...
SOSP
1993
ACM
13 years 11 months ago
1993
ACM
Research can rarely be performed on large-scale, distributed systems at the level of thousands of workstations. In this paper, we describe the motivating constraints, design princ...