339 search results - page 46 / 68 » Noise-tolerant dynamic circuit design |
ICCAD
2006
IEEE
14 years 6 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
ASPLOS
2010
ACM
14 years 4 months ago
2010
ACM
Data center power infrastructure incurs massive capital costs, which typically exceed energy costs over the life of the facility. To squeeze maximum value from the infrastructure,...
DAC
2008
ACM
14 years 10 months ago
2008
ACM
This paper discusses the use of networks-on-chip (NoCs) consisting of multiple voltage-frequency islands to cope with power consumption, clock distribution and parameter variation...
JSA
2007
13 years 9 months ago
2007
This paper presents a multi-language framework to FPGA hardware development which aims to satisfy the dual requirement of high level hardware design and efficient hardware impleme...
ASYNC
2002
IEEE
14 years 2 months ago
2002
IEEE
In a circuit environment that is becoming increasingly sensitive to dynamic power dissipation and noise, and where cycle time available for control decisions continues to decrease...