339 search results - page 6 / 68 » Noise-tolerant dynamic circuit design |
ISLPED
2006
ACM
14 years 1 months ago
2006
ACM
In this paper, we identify the key challenges that oppose subthreshold circuit design and describe fabricated chips that verify techniques for overcoming the challenges. Categorie...
GLVLSI
2003
IEEE
14 years 19 days ago
2003
IEEE
We introduce a simple hierarchical design technique for using dynamic domino circuits to build high-performance self-timed data path circuits. We wrap the dynamic domino circuit i...
ICCAD
1995
IEEE
13 years 11 months ago
1995
IEEE
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
EH
1999
IEEE
13 years 11 months ago
1999
IEEE
High-level analog circuit design is a complex problem domain in which evolutionary search has recently produced encouraging results. However, little is known about how to best str...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
—Increasing power density causes die overheating due to limited cooling capacity of the package. Conventional thermal management techniques e.g. logic shutdown, clock gating, fre...