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» Non-cycle-accurate sequential equivalence checking
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ISQED
2008
IEEE
117views Hardware» more  ISQED 2008»
14 years 2 months ago
A Basis for Formal Robustness Checking
Correct input/output behavior of circuits in presence of internal malfunctions becomes more and more important. But reliable and efficient methods to measure this robustness are ...
Görschwin Fey, Rolf Drechsler
GLVLSI
2005
IEEE
85views VLSI» more  GLVLSI 2005»
14 years 1 months ago
Utilizing don't care states in SAT-based bounded sequential problems
Boolean Satisfiability (SAT) solvers are popular engines used throughout the verification world. Bounded sequential problems such as bounded model checking and bounded sequentia...
Sean Safarpour, Görschwin Fey, Andreas G. Ven...
ISSTA
2006
ACM
14 years 1 months ago
Using model checking with symbolic execution to verify parallel numerical programs
We present a method to verify the correctness of parallel programs that perform complex numerical computations, including computations involving floating-point arithmetic. The me...
Stephen F. Siegel, Anastasia Mironova, George S. A...
DAC
2008
ACM
14 years 9 months ago
Construction of concrete verification models from C++
C++ based verification methodologies are now emerging as the preferred method for SOC design. However most of the verification involving the C++ models are simulation based. The c...
Malay Haldar, Gagandeep Singh, Saurabh Prabhakar, ...
ENTCS
2007
137views more  ENTCS 2007»
13 years 7 months ago
Formal Sequentialization of Distributed Systems via Program Rewriting
Formal sequentialization is introduced as a rewriting process for the reduction of parallelism and internal communication statements of distributed imperative programs. It constru...
Miquel Bertran, Francesc-Xavier Babot, August Clim...