32 search results - page 4 / 7 » Non-cycle-accurate sequential equivalence checking |
CAV
2008
Springer
13 years 10 months ago
2008
Springer
Power gating is a technique for low power design in which whole sections of the chip are powered off when they are not needed, and powered back on when they are. Functional correct...
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
The process of sequential redundancy identification is the cornerstone of sequential synthesis and equivalence checking frameworks. The scalability of the proof obligations inhere...
DAC
2007
ACM
13 years 12 months ago
2007
ACM
It has long been the practice to create models in C or C++ for architectural studies, software prototyping and RTL verification in the design of Systems-on-Chip (SoC). It is often...
ENTCS
2008
13 years 8 months ago
2008
The verification of quantitative aspects like performance and dependability by means of model checking has become an important and vivid area of research over the past decade. An ...