Sciweavers

325 search results - page 14 / 65
» Non-uniform Instruction Scheduling
Sort
View
FCCM
2006
IEEE
144views VLSI» more  FCCM 2006»
14 years 1 months ago
Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA
In this paper, we investigate a combination of two techniques — instruction coding and instruction re-ordering — for optimizing energy in embedded processor control. We presen...
Robert G. Dimond, Oskar Mencer, Wayne Luk
EGH
2004
Springer
14 years 24 days ago
Mio: fast multipass partitioning via priority-based instruction scheduling
Real-time graphics hardware continues to offer improved resources for programmable vertex and fragment shaders. However, shader programmers continue to write shaders that require ...
Andrew Riffel, Aaron E. Lefohn, Kiril Vidimce, Mar...
MICRO
1996
IEEE
81views Hardware» more  MICRO 1996»
13 years 11 months ago
Instruction Scheduling and Executable Editing
Modern microprocessors offer more instruction-level parallelism than most programs and compilers can currently exploit. The resulting disparity between a machine's peak and a...
Eric Schnarr, James R. Larus
IEEEPACT
2003
IEEE
14 years 20 days ago
Efficient Resource Management during Instruction Scheduling for the EPIC Architecture
Effective modeling and management of hardware resources have always been critical toward generating highly efficient code in static compilers. With Just-In-Time compilation and dy...
Dong-yuan Chen, Lixia Liu, Chen Fu, Shuxin Yang, C...