325 search results - page 24 / 65 » Non-uniform Instruction Scheduling |
EUROPAR
2001
Springer
13 years 12 months ago
2001
Springer
Operand bypass logic might be one of the critical structures for future microprocessors to achieve high clock speed. The delay of the logic imposes the execution time budget to be ...
ICS
1999
Tsinghua U.
13 years 11 months ago
1999
Tsinghua U.
Memory operations remain a significant bottleneck in dynamically scheduled pipelined processors, due in part to the inability to statically determine the existence of memory addr...
ISSS
1996
IEEE
13 years 11 months ago
1996
IEEE
The application range of the embedded computing is going to cover the majority of the market products spanning from consumer electronic, automotive, telecom and process control. F...
CASES
2008
ACM
13 years 9 months ago
2008
ACM
While customizable processors aim at combining the flexibility of general purpose processors with the speed and power advantages of custom circuits, commercially available process...
ICCD
2003
IEEE
14 years 4 months ago
2003
IEEE
The VLIW processors with static instruction scheduling and thus deterministic execution times are very suitable for highperformance real-time DSP applications. But the two major w...