325 search results - page 52 / 65 » Non-uniform Instruction Scheduling |
IEEECIT
2010
IEEE
13 years 5 months ago
2010
IEEE
—The relevance of instruction parallelization and optimal event scheduling is currently increasing. In particular, because of the high amount of computational power available tod...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
The challenge of verifying a modern microprocessor design is an overwhelming one: Increasingly complex micro-architectures combined with heavy time-to-market pressure have forced ...
ISCA
2000
IEEE
13 years 11 months ago
2000
IEEE
Our program benchmarks and simulations of novel circuits indicate that large-window processors are feasible. Using our redesigned superscalar components, a large-window processor ...
EUROPAR
1999
Springer
13 years 11 months ago
1999
Springer
Processor cycle time continues to decrease faster than main memory access times, placing higher demands on cache memory hierarchy performance. To meet these demands, conventional ...
JEC
2006
13 years 7 months ago
2006
During the last two decades, Single Instruction Multiple Data (SIMD) processors have become important architectures in embedded systems for image processing applications. The main ...