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ISCA
2000
IEEE

Circuits for wide-window superscalar processors

14 years 4 months ago
Circuits for wide-window superscalar processors
Our program benchmarks and simulations of novel circuits indicate that large-window processors are feasible. Using our redesigned superscalar components, a large-window processor implemented in today’s technology can achieve an increase of 10–60% (geometric mean of 31%) in program speed compared to today’s processors. The processor operates at clock speeds comparable to today’s processors, but achieves significantly higher ILP. To measure the impact of a large window on clock speed, we design and simulate new implementations of the logic components that most limit the critical path of our large-window processor: the schedule logic and the wake-up logic. We use log-depth cyclic segmented prefix (CSP) circuits to reimplement these components. Our layouts and simulations of critical paths through these circuits indicate that our large-window processor could be clocked at frequencies exceeding 500MHz in today’s technology. Our commit logic and rename logic can also run at thes...
Dana S. Henry, Bradley C. Kuszmaul, Gabriel H. Loh
Added 31 Jul 2010
Updated 31 Jul 2010
Type Conference
Year 2000
Where ISCA
Authors Dana S. Henry, Bradley C. Kuszmaul, Gabriel H. Loh, Rahul Sami
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