7 search results - page 1 / 2 » Non-uniform power access in large caches with low-swing wire... |
ISCA
2007
IEEE
14 years 1 months ago
2007
IEEE
The ever increasing sizes of on-chip caches and the growing domination of wire delay necessitate significant changes to cache hierarchy design methodologies. Many recent proposal...
EUROPAR
2009
Springer
13 years 11 months ago
2009
Springer
In response to the constant increase in wire delays, Non-Uniform Cache Architecture (NUCA) has been introduced as an effective memory model for dealing with growing memory latenci...
HIPC
2009
Springer
13 years 4 months ago
2009
Springer
Modern processors dedicate more than half their chip area to large L2 and L3 caches and these caches contribute significantly to the total processor power. A large cache is typica...
MICRO
2003
IEEE
14 years 2 days ago
2003
IEEE
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
DATE
2009
IEEE
14 years 1 months ago
2009
IEEE
Abstract—To deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between...