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» Novel CNTFET-based Reconfigurable Logic Gate Design
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GECCO
2009
Springer
130views Optimization» more  GECCO 2009»
14 years 3 months ago
Liposome logic
VLSI research, in its continuous push toward further miniaturisation, is seeking to break through the limitations of current circuit manufacture techniques by moving towards biomi...
James Smaldon, Natalio Krasnogor, Alexander Camero...
VLSID
2008
IEEE
149views VLSI» more  VLSID 2008»
14 years 8 months ago
NBTI Degradation: A Problem or a Scare?
Negative Bias Temperature Instability (NBTI) has been identified as a major and critical reliability issue for PMOS devices in nano-scale designs. It manifests as a negative thres...
Kewal K. Saluja, Shriram Vijayakumar, Warin Sootka...
FPL
2003
Springer
81views Hardware» more  FPL 2003»
14 years 1 months ago
A TCP/IP Based Multi-device Programming Circuit
This paper describes a lightweight Field Programmable Gate Array (FPGA) circuit design that supports the simultaneous programming of multiple devices at different locations throug...
David V. Schuehler, Harvey Ku, John W. Lockwood
DAC
2009
ACM
14 years 9 months ago
Event-driven gate-level simulation with GP-GPUs
Logic simulation is a critical component of the design tool flow in modern hardware development efforts. It is used widely ? from high-level descriptions down to gate-level ones ?...
Debapriya Chatterjee, Andrew DeOrio, Valeria Berta...
ASYNC
2002
IEEE
112views Hardware» more  ASYNC 2002»
14 years 1 months ago
A Negative-Overhead, Self-Timed Pipeline
This paper presents a novel variation of wave pipelining that we call “surfing.” In previous wave pipelined designs, timing uncertainty grows monotonically as events propagat...
Mark R. Greenstreet, Brian D. Winters