94 search results - page 5 / 19 » Novel CNTFET-based Reconfigurable Logic Gate Design |
ITC
2003
IEEE
14 years 1 months ago
2003
IEEE
In a scan-based system with a large number of flip-flops, a major component of power is consumed during scanshift and clocking operation in test mode. In this paper, a novel scan-...
CODES
2009
IEEE
14 years 5 days ago
2009
IEEE
Field-Programmable Gate Arrays (FPGAs) have become promising mapping fabric for the implementation of System-on-Chip (SoC) platforms, due to their large capacity and their enhance...
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
— Clock power consumes a significant fraction of total power dissipation in high speed precharge/evaluate logic styles. In this paper, we present a novel low-cost design methodol...
CIT
2006
Springer
14 years 3 days ago
2006
Springer
IEEE 754r is the ongoing revision to the IEEE 754 floating point standard. A major enhancement to the standard is the addition of decimal format, thus the design of BCD arithmetic...
ISMVL
2008
IEEE
14 years 2 months ago
2008
IEEE
Abstract—This paper presents fundamental logic structures designed using novel quantum dot gate FETs with three-state characteristics. This three-state FET manifests itself as a ...