129 search results - page 24 / 26 » Novel Design Methodology for High-Performance XOR-XNOR Circu... |
VTS
2007
IEEE
14 years 2 months ago
2007
IEEE
In this paper, a novel test point insertion methodology is presented for RTL designs that aims to reduce the data volume of scan-based transition delay tests. Test points are iden...
VTS
2000
IEEE
14 years 28 days ago
2000
IEEE
The performance of deep sub-micron designs can be affected by various parametric variations, manufacturing defects, noise or even modeling errors that are all statistical in natur...
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper proposes a novel HW/SW co-simulation approach that minimizes the impact on software designers. We propose a SystemC-based system that enables the software team to test ...
ISPD
2003
ACM
14 years 1 months ago
2003
ACM
For multi-gigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles. In this paper, we propose a regular distributed register ...
IPPS
2007
IEEE
14 years 2 months ago
2007
IEEE
Fast hardware turnover in supercomputing centers, stimulated by rapid technological progress, results in high heterogeneity among HPC platforms, and necessitates that applications...