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VLSI
2010
Springer
13 years 4 months ago
Local Biasing and the Use of Nullator-Norator Pairs in Analog Circuits Designs
Although local biasing of components used in an analog circuit is shown to be a very attractive design methodology, significantly simplifying the design procedure [3], it makes the...
Reza Hashemian
VLSID
2005
IEEE
223views VLSI» more  VLSID 2005»
14 years 10 months ago
A New CMOS Current Conveyors Based Translinear Loop for Log-Domain Circuit Design
A novel topology for Translinear (TL) loops comprising of CMOS Second Generation Current Conveyors (CC-II) and diodes is proposed. The proposed methodology opens a new paradigm to...
Debashis Dutta, Wouter A. Serdijn, Swapna Banerjee...
ASPDAC
2006
ACM
117views Hardware» more  ASPDAC 2006»
14 years 3 months ago
Signal-path driven partition and placement for analog circuit
This paper advances a new methodology based on signal-path information to resolve the problem of device-level placement for analog layout. This methodology is mainly based on three...
Di Long, Xianlong Hong, Sheqin Dong
GLVLSI
2007
IEEE
140views VLSI» more  GLVLSI 2007»
14 years 4 months ago
Structured and tuned array generation (STAG) for high-performance random logic
Regularly structured design techniques can combat complexity on a variety of fronts. We present the Structured and Tuned Array Generation (STAG) design methodology, which provides...
Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kos...
ICCD
1997
IEEE
87views Hardware» more  ICCD 1997»
14 years 2 months ago
Synthesizing Iterative Functions into Delay-Insensitive Tree Circuits
Speed, cost and correctness may be the most important factors in designing a digital system. This paper proposes a novel and general methodology to synthesize iterative functions ...
Fu-Chiung Cheng