980 search results - page 63 / 196 » Novel Test Pattern Generators for Pseudo-Exhaustive Testing |
ASPDAC
2001
ACM
14 years 22 days ago
2001
ACM
Abstract--We present a processor-programmable built-in selftest (BIST) scheme suitable for embedded memory testing in the system-on-a-chip (SOC) environment. The proposed BIST circ...
DAC
2009
ACM
14 years 10 months ago
2009
ACM
The discrepancy between integrated circuits' activities in normal functional mode and that in structural test mode has an increasing adverse impact on the effectiveness of ma...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
A high-level test synthesis (HLTS) method targeted for delay fault testability is presented. The proposed method, when combined with hierarchical test pattern generation for embed...
DAC
2007
ACM
14 years 10 months ago
2007
ACM
Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can...
IJOE
2007
13 years 9 months ago
2007
: An environment targeted to e-learning is presented for teaching design and test of electronic systems. The environment consists of a set of Java applets, and of web based access ...