Processor-programmable memory BIST for bus-connected embedded memories

Abstract--We present a processor-programmable built-in selftest (BIST) scheme suitable for embedded memory testing in the system-on-a-chip (SOC) environment. The proposed BIST circuit can be programmed via an on-chip microprocessor. Upon receiving the commands from the microprocessor, the BIST circuit generates pre-defined test patterns and compares the memory outputs with the expected outputs. Most popular memory test algorithms can be realized by properly programming the BIST circuit using the processor instructions. Compared with processor-based memory BIST schemes that use an assembly-language program to generate test patterns and compare the memory outputs, the test time of the proposed memory BIST scheme is greatly reduced.

• Type: Conference
• Year: 2001
• Where: ASPDAC
• Authors: Ching-Hong Tsai, Cheng-Wen Wu
• Keywords: ASPDAC 2001, BIST, BIST Circuit, Hardware, Memory Bist Scheme