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» Novel architectures for efficient (m, n) parallel counters
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PVLDB
2008
126views more  PVLDB 2008»
13 years 7 months ago
Parallelizing query optimization
Many commercial RDBMSs employ cost-based query optimization exploiting dynamic programming (DP) to efficiently generate the optimal query execution plan. However, optimization tim...
Wook-Shin Han, Wooseong Kwak, Jinsoo Lee, Guy M. L...
ICS
2007
Tsinghua U.
14 years 1 months ago
An L2-miss-driven early register deallocation for SMT processors
The register file is one of the most critical datapath components limiting the number of threads that can be supported on a Simultaneous Multithreading (SMT) processor. To allow t...
Joseph J. Sharkey, Dmitry V. Ponomarev
CONEXT
2009
ACM
13 years 8 months ago
Cool-Tether: energy efficient on-the-fly wifi hot-spots using mobile phones
We consider the problem of providing ubiquitous yet affordable Internet connectivity to devices at home, at work, and on the move. In this context, we take advantage of two signif...
Ashish Sharma, Vishnu Navda, Ramachandran Ramjee, ...
IJCNN
2007
IEEE
14 years 2 months ago
Implementation of multi-layer leaky integrator networks on a cellular processor array
- We present an application of a massively parallel processor array VLSI circuit to the implementation of neural networks in complex architectural arrangements. The work was motiva...
David R. W. Barr, Piotr Dudek, Jonathan M. Chamber...
DAC
2005
ACM
14 years 8 months ago
Variations-aware low-power design with voltage scaling
We present a new methodology which takes into consideration the effect of Within-Die (WID) process variations on a low-voltage parallel system. We show that in the presence of pro...
Navid Azizi, Muhammad M. Khellah, Vivek De, Farid ...