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CODES
2004
IEEE
13 years 11 months ago
Operation tables for scheduling in the presence of incomplete bypassing
Register bypassing is a powerful and widely used feature in modern processors to eliminate certain data hazards. Although complete bypassing is ideal for performance, bypassing ha...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...
CASES
2006
ACM
13 years 11 months ago
Reaching fast code faster: using modeling for efficient software thread integration on a VLIW DSP
When integrating software threads together to boost performance on a processor with instruction-level parallel processing support, it is rarely clear which code regions should be ...
Won So, Alexander G. Dean
ERCIMDL
2006
Springer
183views Education» more  ERCIMDL 2006»
13 years 11 months ago
Design of a Cross-Media Indexing System
There is a lack of an integrated technology that will increase effective usage of the vast and heterogeneous multi-lingual and multimedia digital content. The need is being express...
Murat Yakici, Fabio Crestani
GECCO
2006
Springer
210views Optimization» more  GECCO 2006»
13 years 11 months ago
Clustering the heap in multi-threaded applications for improved garbage collection
Garbage collection can be a performance bottleneck in large distributed, multi-threaded applications. Applications may produce millions of objects during their lifetimes and may i...
Myra B. Cohen, Shiu Beng Kooi, Witawas Srisa-an
CASES
2001
ACM
13 years 11 months ago
Transparent data-memory organizations for digital signal processors
Today's digital signal processors (DSPs), unlike general-purpose processors, use a non-uniform addressing model in which the primary components of the memory system--the DRAM...
Sadagopan Srinivasan, Vinodh Cuppu, Bruce L. Jacob
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