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VLSID
2007
IEEE
153views VLSI» more  VLSID 2007»
14 years 9 months ago
Extracting Logic Circuit Structure from Conjunctive Normal Form Descriptions
Boolean Satisfiability is seeing increasing use as a decision procedure in Electronic Design Automation (EDA) and other domains. Most applications encode their domain specific cons...
Zhaohui Fu, Sharad Malik
CISIS
2010
IEEE
14 years 3 months ago
Logic-Based Steady-State Analysis and Revision of Metabolic Networks with Inhibition
—This paper presents a qualitative logic-based method for the steady-state analysis and revision of metabolic networks with inhibition. The approach is able to automatically revi...
Oliver Ray, Ken E. Whelan, Ross D. King
FTRTFT
1998
Springer
14 years 1 months ago
Operational and Logical Semantics for Polling Real-Time Systems
PLC-Automata are a class of real-time automata suitable to describe the behavior of polling real-time systems. PLC-Automata can be compiled to source code for PLCs, a hardware wide...
Henning Dierks, Ansgar Fehnker, Angelika Mader, Fr...
ASPDAC
2010
ACM
137views Hardware» more  ASPDAC 2010»
13 years 6 months ago
Managing verification error traces with bounded model debugging
Managing long verification error traces is one of the key challenges of automated debugging engines. Today, debuggers rely on the iterative logic array to model sequential behavior...
Sean Safarpour, Andreas G. Veneris, Farid N. Najm
JUCS
2006
131views more  JUCS 2006»
13 years 8 months ago
Verification of CRWL Programs with Rewriting Logic
Abstract: We present a novel approach to the verification of functional-logic programs. For our verification purposes, equational reasoning is not valid due to the presence of non-...
José Miguel Cleva, Isabel Pita