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GLVLSI
2007
IEEE
194views VLSI» more  GLVLSI 2007»
15 years 7 months ago
Probabilistic maximum error modeling for unreliable logic circuits
Reliability modeling and evaluation is expected to be one of the major issues in emerging nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for gate f...
Karthikeyan Lingasubramanian, Sanjukta Bhanja
SDM
2007
SIAM
104views Data Mining» more  SDM 2007»
15 years 4 months ago
Boosting Optimal Logical Patterns Using Noisy Data
We consider the supervised learning of a binary classifier from noisy observations. We use smooth boosting to linearly combine abstaining hypotheses, each of which maps a subcube...
Noam Goldberg, Chung-chieh Shan
DATE
2009
IEEE
106views Hardware» more  DATE 2009»
15 years 10 months ago
Debugging of Toffoli networks
—Intensive research is performed to find post-CMOS technologies. A very promising direction based on reversible logic are quantum computers. While in the domain of reversible lo...
Robert Wille, Daniel Große, Stefan Frehse, G...
AAAI
2011
14 years 3 months ago
Preferred Explanations: Theory and Generation via Planning
In this paper we examine the general problem of generating preferred explanations for observed behavior with respect to a model of the behavior of a dynamical system. This problem...
Shirin Sohrabi, Jorge A. Baier, Sheila A. McIlrait...
MST
2010
122views more  MST 2010»
14 years 10 months ago
Self-Referential Justifications in Epistemic Logic
This paper is devoted to the study of self-referential proofs and/or justifications, i.e., valid proofs that prove statements about these same proofs. The goal is to investigate wh...
Roman Kuznets