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ISCAS
1999
IEEE
106views Hardware» more  ISCAS 1999»
14 years 1 months ago
Test pattern generation for width compression in BIST
The main objectives of Built-In Self Test (BIST) are the design of test pattern generator circuits which achieve the highest fault coverage, require the shortest sequence of test ...
Paulo F. Flores, Horácio C. Neto, K. Chakra...
SLIP
2009
ACM
14 years 3 months ago
Is overlay error more important than interconnect variations in double patterning?
Double patterning lithography seems to be a prominent choice for 32nm and 22nm technologies. Double patterning lithography techniques require additional masks for a single interco...
Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topalog...
ICPR
2006
IEEE
14 years 2 months ago
Multiscale Feature Extraction of Finger-Vein Patterns Based on Curvelets and Local Interconnection Structure Neural Network
In this paper, we originally propose a multiscale feature extraction method of finger-vein patterns based on curvelets and local interconnection structure neural networks. The cur...
Zhongbo Zhang, Siliang Ma, Xiao Han
EWSN
2006
Springer
14 years 8 months ago
Results of Bit Error Measurements with Sensor Nodes and Casuistic Consequences for Design of Energy-Efficient Error Control Sche
For the proper design of energy-efficient error control schemes some insight into channel error patterns is needed. This paper presents bit error and packet loss measurements taken...
Andreas Willig, Robert Mitschke
AUTOID
2005
IEEE
14 years 2 months ago
Impedance Matching Concepts in RFID Transponder Design
In this paper, we analyze impedance matching concepts in passive radio frequency identification (RFID) transponders, which are powered by the incoming RF energy and consist of an...
K. V. S. Rao, Pavel V. Nikitin, Sander F. Lam