We provide a new theoretical framework for constructing Steiner routing trees with minimum Elmore delay. Earlier work [3, 13] has established Elmore delay as a high delity estima...
Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCo...
Interconnect optimization for VLSI circuits has received wide attention. To model routing surfaces, multiple circuit layers are freabstracted as a single rectilinear plane, ignori...
We present a polynomial-time approximation scheme (PTAS) for the Steiner tree problem with polygonal obstacles in the plane with running time O(n log2 n), where n denotes the numb...
: We discuss a new approach to constructing the rectilinear Steiner tree (RST) of a given set of points in the plane, starting from a minimum spanning tree (MST). The main idea in ...