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HIPEAC
2005
Springer
14 years 1 months ago
Enhancing Network Processor Simulation Speed with Statistical Input Sampling
Abstract. While cycle-accurate simulation tools have been widely used in modeling high-performance processors, such an approach can be hindered by the increasing complexity of the ...
Jia Yu, Jun Yang 0002, Shaojie Chen, Yan Luo, Laxm...
CODES
2003
IEEE
14 years 26 days ago
Schedule-aware performance estimation of communication architecture for efficient design space exploration
In this paper, we are concerned about the performance estimation of bus-based architectures assuming that the task partitioning on the processing components is already determined....
Sungchan Kim, Chaeseok Im, Soonhoi Ha
CODES
1999
IEEE
13 years 12 months ago
An MPEG-2 decoder case study as a driver for a system level design methodology
We present a case study on the design of a heterogeneous architecture for MPEG-2 video decoding. The primary objective of the case study is the validation of the SPADE methodology...
Pieter van der Wolf, Paul Lieverse, Mudit Goel, Da...
ICSE
1999
IEEE-ACM
13 years 11 months ago
Dynamically Discovering Likely Program Invariants to Support Program Evolution
ÐExplicitly stated program invariants can help programmers by identifying program properties that must be preserved when modifying code. In practice, however, these invariants are...
Michael D. Ernst, Jake Cockrell, William G. Griswo...
ISCA
1992
IEEE
125views Hardware» more  ISCA 1992»
13 years 11 months ago
Limits of Control Flow on Parallelism
This paper discusses three techniques useful in relaxing the constraints imposed by control flow on parallelism: control dependence analysis, executing multiple flows of control s...
Monica S. Lam, Robert P. Wilson