In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
Abstract. We study the decidability and complexity of verification problems for timed automata over time intervals of fixed, bounded length. One of our main results is that time-bo...
Web applications are the most common way to make services and data available on the Internet. Unfortunately, with the increase in the number and complexity of these applications, ...
Viktoria Felmetsger, Ludovico Cavedon, Christopher...
We present dcl-pc: a dynamic logic of delegation and cooperation. The logical foundation of dcl-pc is cl-pc, a logic for reasoning about cooperation in which the powers of agents ...
— Semi-formal verification based on symbolic simulation offers a good compromise between formal model checking and numerical simulation. The generation of functional test vector...
Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre