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MICRO
2010
IEEE
215views Hardware» more  MICRO 2010»
13 years 9 months ago
A Task-Centric Memory Model for Scalable Accelerator Architectures
This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit ...
John H. Kelm, Daniel R. Johnson, Steven S. Lumetta...
CODES
2006
IEEE
14 years 5 months ago
Automatic generation of transaction level models for rapid design space exploration
Transaction-level modeling has been touted to improve simulation performance and modeling efficiency for early design space exploration. But no tools are available to generate suc...
Dongwan Shin, Andreas Gerstlauer, Junyu Peng, Rain...
FMSD
2006
83views more  FMSD 2006»
13 years 11 months ago
A Framework for Modeling the Distributed Deployment of Synchronous Designs
Synchronous specifications are appealing in the design of large scale hardware and software systems because of their properties that facilitate verification and synthesis. When the...
Luca P. Carloni, Alberto L. Sangiovanni-Vincentell...
VLSI
2010
Springer
13 years 9 months ago
Design of low-complexity and high-speed digital Finite Impulse Response filters
—In this paper, we introduce a design methodology to implement low-complexity and high-speed digital Finite Impulse Response (FIR) filters. Since FIR filters suffer from a larg...
Diego Jaccottet, Eduardo Costa, Levent Aksoy, Paul...
DAC
2000
ACM
14 years 3 months ago
Using general-purpose programming languages for FPGA design
ct General-purpose programming languages (GPL) are effective vehicles for FPGA design because they are easy to use, extensible, widely available, and can be used to describe both t...
Brad L. Hutchings, Brent E. Nelson