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» On Detecting Bridges Causing Timing Failures
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WCET
2007
13 years 8 months ago
Finding DU-Paths for Testing of Multi-Tasking Real-Time Systems using WCET Analysis
Memory corruption is one of the most common software failures. For sequential software and multitasking software with synchronized data accesses, it has been shown that program fa...
Daniel Sundmark, Anders Pettersson, Christer Sandb...
DATE
2010
IEEE
161views Hardware» more  DATE 2010»
14 years 13 days ago
Aging-resilient design of pipelined architectures using novel detection and correction circuits
—Time-dependent performance degradation due to transistor aging caused by mechanisms such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) is one o...
Hamed F. Dadgour, Kaustav Banerjee
DSN
2003
IEEE
14 years 19 days ago
Evaluation of Fault Handling of the Time-Triggered Architecture with Bus and Star Topology
Arbitrary faults of a single node in a time-triggered architecture (TTA) bus topology system may cause error propagation to correct nodes and may lead to inconsistent system state...
Astrit Ademaj, Håkan Sivencrona, Günthe...
ITC
2000
IEEE
93views Hardware» more  ITC 2000»
13 years 11 months ago
Stuck-fault tests vs. actual defects
This paper studies some manufacturing test data collected for an experimental digital IC. Test results for a large variety of single-stuck fault based test sets are shown and comp...
Edward J. McCluskey, Chao-Wen Tseng
VTS
1996
IEEE
114views Hardware» more  VTS 1996»
13 years 11 months ago
Quantitative analysis of very-low-voltage testing
Some weak static CMOS chips can be detected by testing them with a very low supply voltage -- between 2 and 2.5 times the threshold voltage Vt of the transistors. A weak chip is o...
Jonathan T.-Y. Chang, Edward J. McCluskey