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» On Fault Testing for Reversible Circuits
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TCAD
2008
114views more  TCAD 2008»
13 years 8 months ago
Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns
At-speed functional testing, delay testing, and n-detection test sets are being used today to detect deep submicrometer defects. However, the resulting test data volumes are too hi...
Zhanglei Wang, Krishnendu Chakrabarty
ITC
2002
IEEE
99views Hardware» more  ITC 2002»
14 years 1 months ago
Verifying Properties Using Sequential ATPG
This paper develops a novel approach for formally verifying both safety and liveness properties of designs using sequential ATPG tools. The properties are automatically mapped int...
Jacob A. Abraham, Vivekananda M. Vedula, Daniel G....
VLSID
2005
IEEE
131views VLSI» more  VLSID 2005»
14 years 9 months ago
Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
Lei Li, Krishnendu Chakrabarty, Seiji Kajihara, Sh...
DSD
2007
IEEE
98views Hardware» more  DSD 2007»
14 years 3 months ago
Fault Diagnosis in Integrated Circuits with BIST
This paper presents an optimized fault diagnosing procedure applicable in Built-in Self-Test environments. Instead of the known approach based on a simple bisection of patterns in...
Raimund Ubar, Sergei Kostin, Jaan Raik, Teet Evart...
ICCAD
2006
IEEE
126views Hardware» more  ICCAD 2006»
14 years 5 months ago
Exploring linear structures of critical path delay faults to reduce test efforts
It has been shown that the delay of a target path can be composed linearly of other path delays. If the later paths are robustly testable (with known delay values), the target pat...
Shun-Yen Lu, Pei-Ying Hsieh, Jing-Jia Liou