216 search results - page 19 / 44 » On High-Bandwidth Data Cache Design for Multi-Issue Processo... |
CODES
2007
IEEE
14 years 2 months ago
2007
IEEE
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
ICS
2010
Tsinghua U.
13 years 10 months ago
2010
Tsinghua U.
The growing influence of wire delay in cache design has meant that access latencies to last-level cache banks are no longer constant. Non-Uniform Cache Architectures (NUCAs) have ...
ISLPED
2009
ACM
14 years 2 months ago
2009
ACM
The design trend of caches in modern processors continues to increase their capacity with higher associativity to cope with large data footprint and take advantage of feature size...
EUROPAR
2009
Springer
13 years 11 months ago
2009
Springer
The Cell Broadband Engine (Cell BE) is a heterogeneous multi-core processor specifically designed to exploit thread-level parallelism. Its memory model comprehends a common shared ...
ISLPED
2003
ACM
14 years 1 months ago
2003
ACM
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of ...