216 search results - page 27 / 44 » On High-Bandwidth Data Cache Design for Multi-Issue Processo... |
ECRTS
2007
IEEE
14 years 2 months ago
2007
IEEE
Of late, there has been a considerable interest in models, algorithms and methodologies specifically targeted towards designing hardware and software for streaming applications. ...
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
The widespread use of multicore processors has dramatically increased the demands on high bandwidth and large capacity from memory systems. In a conventional DDR2/DDR3 DRAM memory...
ISVLSI
2003
IEEE
14 years 1 months ago
2003
IEEE
Previous work has shown that cache line sizes impact performance differently for different desktop programs – some programs work better with small line sizes, others with larger...
MICRO
1994
IEEE
13 years 12 months ago
1994
IEEE
Multiple issue of instructions occurs in superscalar and VLIW machines. This paper investigates a third type of machine design, which combines the advantages of code compatibility...
PPOPP
2009
ACM
14 years 8 months ago
2009
ACM
A stream processor executes an application that has been decomposed into a sequence of kernels that operate on streams of data elements. During the execution of a kernel, all stre...