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ICCD
2001
IEEE
106views Hardware» more  ICCD 2001»
14 years 4 months ago
A Low-Power Cache Design for CalmRISCTM-Based Systems
Lowering power consumption in microprocessors, whether used in portables or not, has now become one of the most critical design concerns. On-chip cache memories tend to occupy dom...
Sangyeun Cho, Wooyoung Jung, Yongchun Kim, Seh-Woo...
TVLSI
2008
150views more  TVLSI 2008»
13 years 7 months ago
Data Memory Subsystem Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance o...
M. Bennaser, Yao Guo, Csaba Andras Moritz
ICCD
2004
IEEE
114views Hardware» more  ICCD 2004»
14 years 4 months ago
Low Energy, Highly-Associative Cache Design for Embedded Processors
Many embedded processors use highly associative data caches implemented using a CAM-based tag search. When high-associativity is desirable, CAM designs can offer performance advan...
Alexander V. Veidenbaum, Dan Nicolaescu
HIPEAC
2005
Springer
14 years 1 months ago
Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation
Increasingly tight energy design goals require processor architects to rethink the organizational structure of microarchitectural resources. In this paper, we examine a new multila...
Michael J. Geiger, Sally A. McKee, Gary S. Tyson
CODES
2010
IEEE
13 years 5 months ago
Dynamic, non-linear cache architecture for power-sensitive mobile processors
Today, mobile smartphones are expected to be able to run the same complex, algorithm-heavy, memory-intensive applications that were originally designed and coded for generalpurpos...
Garo Bournoutian, Alex Orailoglu