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» On Modeling Cross-Talk Faults
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VTS
2002
IEEE
120views Hardware» more  VTS 2002»
14 years 1 months ago
Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
Madhu K. Iyer, Kwang-Ting Cheng
ICCD
2008
IEEE
202views Hardware» more  ICCD 2008»
14 years 5 months ago
CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework
— Extreme scaling practices in silicon technology are quickly leading to integrated circuit components with limited reliability, where phenomena such as early-transistor failures...
Andrea Pellegrini, Kypros Constantinides, Dan Zhan...
ISCA
2007
IEEE
182views Hardware» more  ISCA 2007»
14 years 3 months ago
Configurable isolation: building high availability systems with commodity multi-core processors
High availability is an increasingly important requirement for enterprise systems, often valued more than performance. Systems designed for high availability typically use redunda...
Nidhi Aggarwal, Parthasarathy Ranganathan, Norman ...
DSN
2006
IEEE
14 years 3 months ago
Assessment of the Effect of Memory Page Retirement on System RAS Against Hardware Faults
The Solaris 10 Operating System includes a number of new features for predictive self-healing. One such feature is the ability of the Fault Management software to diagnose memory ...
Dong Tang, Peter Carruthers, Zuheir Totari, Michae...
ITC
2003
IEEE
139views Hardware» more  ITC 2003»
14 years 2 months ago
Fault Pattern Oriented Defect Diagnosis for Memories
Failure analysis (FA) and diagnosis of memory cores plays a key role in system-on-chip (SOC) product development and yield ramp-up. Conventional FA based on bitmaps and the experi...
Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung...