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» On Modeling Cross-Talk Faults
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GLVLSI
2002
IEEE
136views VLSI» more  GLVLSI 2002»
14 years 1 months ago
Test generation for resistive opens in CMOS
This paper develops new techniques for detecting both stuck-open faults and resistive open faults, which result in increased delays along some paths. The improved detection of CMO...
Arun Krishnamachary, Jacob A. Abraham
COMPSAC
2011
IEEE
12 years 8 months ago
Precise Propagation of Fault-Failure Correlations in Program Flow Graphs
Abstract—Statistical fault localization techniques find suspicious faulty program entities in programs by comparing passed and failed executions. Existing studies show that such ...
Zhenyu Zhang, W. K. Chan, T. H. Tse, Bo Jiang
IOLTS
2006
IEEE
101views Hardware» more  IOLTS 2006»
14 years 2 months ago
Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor
— Delay failures are becoming a dominant failure mechanism in nanometer technologies. Diagnosis of such failures is important to ensure yield and robustness of the design. Howeve...
Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury,...
VTS
1996
IEEE
112views Hardware» more  VTS 1996»
14 years 23 days ago
Optimal voltage testing for physically-based faults
In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus on two f...
Yuyun Liao, D. M. H. Walker
ETS
2006
IEEE
110views Hardware» more  ETS 2006»
14 years 2 months ago
Deterministic Logic BIST for Transition Fault Testing
BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applie...
Valentin Gherman, Hans-Joachim Wunderlich, Jü...