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» On Parallel Pseudo-Random Number Generation
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ISCA
2006
IEEE
187views Hardware» more  ISCA 2006»
14 years 3 months ago
A Case for MLP-Aware Cache Replacement
Performance loss due to long-latency memory accesses can be reduced by servicing multiple memory accesses concurrently. The notion of generating and servicing long-latency cache m...
Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu,...
HPDC
2005
IEEE
14 years 3 months ago
Genetic algorithm based automatic data partitioning scheme for HPF
good data partitioning scheme is the need of the time. However it is very diflcult to arrive at a good solution as the number of possible dutupartitionsfor a given real lifeprogra...
Sunil Kumar Anand, Y. N. Srikant
ISCA
2002
IEEE
104views Hardware» more  ISCA 2002»
13 years 9 months ago
Speculative Dynamic Vectorization
Traditional vector architectures have shown to be very effective for regular codes where the compiler can detect data-level parallelism. However, this SIMD parallelism is also pre...
Alex Pajuelo, Antonio González, Mateo Valer...
CF
2010
ACM
14 years 3 months ago
Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cach
As the number of transistors on a chip doubles with every technology generation, the number of on-chip cores also increases rapidly, making possible in a foreseeable future to des...
Pierre Michaud, Yiannakis Sazeides, André S...
BMCBI
2008
149views more  BMCBI 2008»
13 years 8 months ago
MD-SeeGH: a platform for integrative analysis of multi-dimensional genomic data
Background: Recent advances in global genomic profiling methodologies have enabled multidimensional characterization of biological systems. Complete analysis of these genomic prof...
Bryan Chi, Ronald J. deLeeuw, Bradley P. Coe, Raym...