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DDECS
2006
IEEE
79views Hardware» more  DDECS 2006»
14 years 1 months ago
Multiple-Vector Column-Matching BIST Design Method
- Extension of a BIST design algorithm is proposed in this paper. The method is based on a synthesis of a combinational block - the decoder, transforming pseudo-random code words i...
Petr Fiser, Hana Kubatova
MFCS
2005
Springer
14 years 1 months ago
Autoreducibility, Mitoticity, and Immunity
We show the following results regarding complete sets. • NP-complete sets and PSPACE-complete sets are many-one autoreducible. • Complete sets of any level of PH, MODPH, or th...
Christian Glaßer, Mitsunori Ogihara, Aduri P...
ICRA
2003
IEEE
119views Robotics» more  ICRA 2003»
14 years 23 days ago
Incremental low-discrepancy lattice methods for motion planning
We present deterministic sequences for use in sampling-based approaches to motion planning. They simultaneously combine the qualities found in many other sequences: i) the increme...
Stephen R. Lindemann, Steven M. LaValle
FOCS
2000
IEEE
13 years 12 months ago
Zaps and Their Applications
A zap is a two-round, public coin witness-indistinguishable protocol in which the first round, consisting of a message from the verifier to the prover, can be fixed “once and...
Cynthia Dwork, Moni Naor
DATE
1998
IEEE
110views Hardware» more  DATE 1998»
13 years 11 months ago
Scheduling and Module Assignment for Reducing Bist Resources
Built-in self-test BIST techniques modify functional hardware to give a data path the capability to test itself. The modi cation of data path registers into registers BIST resourc...
Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breue...