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EUROPAR
2001
Springer
14 years 2 months ago
Execution Latency Reduction via Variable Latency Pipeline and Instruction Reuse
Operand bypass logic might be one of the critical structures for future microprocessors to achieve high clock speed. The delay of the logic imposes the execution time budget to be ...
Toshinori Sato, Itsujiro Arita
FPGA
2001
ACM
139views FPGA» more  FPGA 2001»
14 years 2 months ago
A memory coherence technique for online transient error recovery of FPGA configurations
The partial reconfiguration feature of some of the currentgeneration Field Programmable Gate Arrays (FPGAs) can improve dependability by detecting and correcting errors in onchip ...
Wei-Je Huang, Edward J. McCluskey
ICOIN
2001
Springer
14 years 2 months ago
Performance Analysis of QoS Routing with Network Dependant Delay Cost
This paper investigates the problem of path calcul ation of multiple metric routing. Toda ’s Internet routing is based on a single metric path selecting algorithm. Single metric...
Hahnearl Jeon, Sung-Dae Kim, Young Joon Kim, Hyung...
ISAAC
2001
Springer
123views Algorithms» more  ISAAC 2001»
14 years 2 months ago
Labeling Subway Lines
Abstract. Graphical features on map, charts, diagrams and graph drawings usually must be annotated with text labels in order to convey their meaning. In this paper we focus on a pr...
Maria Angeles Garrido, Claudia Iturriaga, Alberto ...
KIVS
2001
Springer
14 years 2 months ago
Real-Time Support on Top of Ethernet
Ethernet is a widely used low-cost networking technology. It however lacks the determinism and resource management features needed to meet realtime requirements of multimedia appli...
Rainer Koster, Thorsten Kramp