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» On Reconfigurable Co-processing Units
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ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
14 years 4 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
DAC
2002
ACM
14 years 8 months ago
Exploiting operation level parallelism through dynamically reconfigurable datapaths
Increasing non-recurring engineering (NRE) and mask costs are making it harder to turn to hardwired Application Specific Integrated Circuit (ASIC) solutions for high performance a...
Zhining Huang, Sharad Malik
IROS
2009
IEEE
150views Robotics» more  IROS 2009»
14 years 2 months ago
AWE: A robotic wall and reconfigurable desk supporting working life in a digital society
—“AWE” is a programmable “Animated Work Environment” supporting everyday human activities, at home, work and school, in an increasingly digital society. AWE features a no...
Keith Evan Green, Ian D. Walker, Leo J. Gugerty, J...
CDES
2006
184views Hardware» more  CDES 2006»
13 years 9 months ago
Compilation for Future Nanocomputer Architectures
Compilation has a long history of translating a programmer's human-readable code into machine instructions designed to make good use of a specific target computer. In this pa...
Thomas P. Way
SAMOS
2004
Springer
14 years 1 months ago
Modeling Loop Unrolling: Approaches and Open Issues
Abstract. Loop unrolling plays an important role in compilation for Reconfigurable Processing Units (RPUs) as it exposes operator parallelism and enables other transformations (e.g...
João M. P. Cardoso, Pedro C. Diniz