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» On Reducing Circuit Malfunctions Caused by Soft Errors
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IOLTS
2006
IEEE
103views Hardware» more  IOLTS 2006»
14 years 1 months ago
Designing Robust Checkers in the Presence of Massive Timing Errors
So far, performance and reliability of circuits have been determined by worst-case characterization of silicon and environmental noise. As new deep sub-micron technologies exacerb...
Frederic Worm, Patrick Thiran, Paolo Ienne
ICCAD
2007
IEEE
103views Hardware» more  ICCAD 2007»
14 years 4 months ago
Enhancing design robustness with reliability-aware resynthesis and logic simulation
While circuit density and power efficiency increase with each major advance in IC technology, reliability with respect to soft errors tends to decrease. Current solutions to this...
Smita Krishnaswamy, Stephen Plaza, Igor L. Markov,...
DFT
2007
IEEE
105views VLSI» more  DFT 2007»
14 years 1 months ago
A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction
Decreasing feature sizes have led to an increased vulnerability of random logic to soft errors. A particle strike may cause a glitch or single event transient (SET) at the output ...
Sybille Hellebrand, Christian G. Zoellin, Hans-Joa...
ISCAS
2003
IEEE
172views Hardware» more  ISCAS 2003»
14 years 23 days ago
Performance modeling of resonant tunneling based RAMs
Tunneling based random-access memories (TRAM’s) have recently garnered a great amount of interests among the memory designers due to their intrinsic merits such as reduced power...
Hui Zhang, Pinaki Mazumder, Li Ding 0002, Kyoungho...
SIGCOMM
2009
ACM
14 years 2 months ago
Cross-layer wireless bit rate adaptation
This paper presents SoftRate, a wireless bit rate adaptation protocol that is responsive to rapidly varying channel conditions. Unlike previous work that uses either frame recepti...
Mythili Vutukuru, Hari Balakrishnan, Kyle Jamieson