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ISCA
2000
IEEE
78views Hardware» more  ISCA 2000»
13 years 12 months ago
On the value locality of store instructions
Value locality, a recently discovered program attribute that describes the likelihood of the recurrence of previously-seen program values, has been studied enthusiastically in the...
Kevin M. Lepak, Mikko H. Lipasti
IPPS
1999
IEEE
13 years 11 months ago
A Graph Based Framework to Detect Optimal Memory Layouts for Improving Data Locality
In order to extract high levels of performance from modern parallel architectures, the effective management of deep memory hierarchies is very important. While architectural advan...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...
PARCO
2003
13 years 8 months ago
Cache Memory Behavior of Advanced PDE Solvers
Three different partial differential equation (PDE) solver kernels are analyzed in respect to cache memory performance on a simulated shared memory computer. The kernels implement...
Dan Wallin, Henrik Johansson, Sverker Holmgren
MICRO
2007
IEEE
139views Hardware» more  MICRO 2007»
14 years 1 months ago
Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors
DRAM memory is a major resource shared among cores in a chip multiprocessor (CMP) system. Memory requests from different threads can interfere with each other. Existing memory acc...
Onur Mutlu, Thomas Moscibroda
ARC
2010
Springer
186views Hardware» more  ARC 2010»
13 years 10 months ago
Application-Specific Signatures for Transactional Memory in Soft Processors
As reconfigurable computing hardware and in particular FPGA-based systems-on-chip comprise an increasing number of processor and accelerator cores, supporting sharing and synchroni...
Martin Labrecque, Mark Jeffrey, J. Gregory Steffan