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ICCD
2006
IEEE
103views Hardware» more  ICCD 2006»
14 years 4 months ago
Reduce Register Files Leakage Through Discharging Cells
— We propose a low-leakage register file cell design based on the observation that the physical registers in a superscalar processor have very short life cycles. When a register...
Lingling Jin, Wei Wu, Jun Yang 0002, Chuanjun Zhan...
MAM
2008
114views more  MAM 2008»
13 years 7 months ago
Asymmetrically banked value-aware register files for low-energy and high-performance
Designing high-performance low-energy register files is of critical importance to the continuation of current performance advances in wide-issue and deeply pipelined superscalar m...
Shuai Wang, Hongyan Yang, Jie S. Hu, Sotirios G. Z...
EUROPAR
2009
Springer
13 years 11 months ago
Dynamic Detection of Uniform and Affine Vectors in GPGPU Computations
Abstract. We present a hardware mechanism which dynamically detects uniform and affine vectors used in Graphics Processing Units, to minimize pressure on the register file and redu...
Sylvain Collange, David Defour, Yao Zhang
ICPP
2006
IEEE
14 years 1 months ago
Address-Value Decoupling for Early Register Deallocation
We propose a series of aggressive register deallocation mechanisms to reduce the register file pressure and increase the parallelism exploited by superscalar microprocessors. Our ...
Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev,...
ISVLSI
2007
IEEE
127views VLSI» more  ISVLSI 2007»
14 years 1 months ago
Asymmetrically Banked Value-Aware Register Files
Designing high-performance low-power register files is of critical importance to the continuation of current performance advances in wide-issue and deeply-pipelined superscalar m...
Shuai Wang, Hongyan Yang, Jie Hu, Sotirios G. Ziav...