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» On Reduction of Lagrange Systems
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FMCAD
1998
Springer
14 years 2 months ago
Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification
We present a new approach to the verification of hardware systems with data dependencies using temporal logic symbolic model checking. As a benchmark we take Tomasulo's algori...
Sergey Berezin, Armin Biere, Edmund M. Clarke, Yun...
ICCAD
1997
IEEE
144views Hardware» more  ICCAD 1997»
14 years 2 months ago
Partial scan delay fault testing of asynchronous circuits
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...
Michael Kishinevsky, Alex Kondratyev, Luciano Lava...
ICCAD
1997
IEEE
97views Hardware» more  ICCAD 1997»
14 years 2 months ago
Low power logic synthesis for XOR based circuits
An abundance of research e orts in low power logic synthesis have so far been focused on and or or nand nor based logic. A typical approach is to rst generate an initial multi-lev...
Unni Narayanan, C. L. Liu
ISER
1997
Springer
86views Robotics» more  ISER 1997»
14 years 2 months ago
Preliminary Experiments with an Actively Tuned Passive Dynamic Running Robot
: This paper describes experiments with an electrically actuated one legged hopping robot, the ARL Monopod. While a spring-mass system, comprised of the leg spring and the body mas...
Mojtaba Ahmadi, Martin Buehler
ASWEC
2007
IEEE
14 years 2 months ago
Managing Conflicts When Using Combination Strategies to Test Software
Testers often represent systems under test in input parameter models. These contain parameters with associated values. Combinations of parameter values, with one value for each pa...
Mats Grindal, Jeff Offutt, Jonas Mellin