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» On Reduction of Lagrange Systems
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VTC
2008
IEEE
102views Communications» more  VTC 2008»
14 years 4 months ago
Channel Prediction Aided Multiuser Transmission in SDMA
— Transmit preprocessing employed at the basestation (BS) has been proposed for simplifying the design of the mobile receiver. Provided that the channel impulse response (CIR) of...
Wei Liu, Lie-Liang Yang, Lajos Hanzo
SMC
2007
IEEE
156views Control Systems» more  SMC 2007»
14 years 4 months ago
Dynamic fusion of classifiers for fault diagnosis
—This paper considers the problem of temporally fusing classifier outputs to improve the overall diagnostic classification accuracy in safety-critical systems. Here, we discuss d...
Satnam Singh, Kihoon Choi, Anuradha Kodali, Krishn...
LCTRTS
2007
Springer
14 years 4 months ago
Compiler-managed partitioned data caches for low power
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlk...
CASES
2006
ACM
14 years 3 months ago
Adapting compilation techniques to enhance the packing of instructions into registers
The architectural design of embedded systems is becoming increasingly idiosyncratic to meet varying constraints regarding energy consumption, code size, and execution time. Tradit...
Stephen Hines, David B. Whalley, Gary S. Tyson
GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
14 years 3 months ago
A first look at the interplay of code reordering and configurable caches
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt