Sciweavers

2452 search results - page 475 / 491
» On Reduction of Lagrange Systems
Sort
View
ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
14 years 2 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
ISCA
2010
IEEE
204views Hardware» more  ISCA 2010»
14 years 2 months ago
Energy proportional datacenter networks
Numerous studies have shown that datacenter computers rarely operate at full utilization, leading to a number of proposals for creating servers that are energy proportional with r...
Dennis Abts, Michael R. Marty, Philip M. Wells, Pe...
CSFW
2002
IEEE
14 years 2 months ago
Capturing Parallel Attacks within the Data Independence Framework
We carry forward the work described in our previous papers [3, 14, 12] on the application of data independence to the model checking of cryptographic protocols using CSP [13] and ...
Philippa J. Broadfoot, A. W. Roscoe
INFOCOM
2002
IEEE
14 years 2 months ago
Optimal Configuration of OSPF Aggregates
—Open Shortest Path First (OSPF) is a popular protocol for routing within an autonomous system (AS) domain. In order to scale for large networks containing hundreds and thousands...
Rajeev Rastogi, Yuri Breitbart, Minos N. Garofalak...
ISCA
2002
IEEE
105views Hardware» more  ISCA 2002»
14 years 2 months ago
Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
Anoop Iyer, Diana Marculescu