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» On Timed Alternating Simulation for Concurrent Timed Games
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JSA
2000
116views more  JSA 2000»
13 years 7 months ago
Distributed vector architectures
Integrating processors and main memory is a promising approach to increase system performance. Such integration provides very high memory bandwidth that can be exploited efficientl...
Stefanos Kaxiras
SENSYS
2010
ACM
13 years 5 months ago
Cooperative transit tracking using smart-phones
Real-time transit tracking is gaining popularity as a means for transit agencies to improve the rider experience. However, many transit agencies lack either the funding or initiat...
Arvind Thiagarajan, James Biagioni, Tomas Gerlich,...
ASPLOS
2009
ACM
14 years 8 months ago
Phantom-BTB: a virtualized branch target buffer design
Modern processors use branch target buffers (BTBs) to predict the target address of branches such that they can fetch ahead in the instruction stream increasing concurrency and pe...
Ioana Burcea, Andreas Moshovos
CHI
2009
ACM
14 years 8 months ago
Focus on driving: how cognitive constraints shape the adaptation of strategy when dialing while driving
We investigate how people adapt their strategy for interleaving multiple concurrent tasks to varying objectives. A study was conducted in which participants drove a simulated vehi...
Duncan P. Brumby, Dario D. Salvucci, Andrew Howes
MICRO
2008
IEEE
118views Hardware» more  MICRO 2008»
14 years 1 months ago
Notary: Hardware techniques to enhance signatures
Hardware signatures have been recently proposed as an efficient mechanism to detect conflicts amongst concurrently running transactions in transactional memory systems (e.g., Bulk...
Luke Yen, Stark C. Draper, Mark D. Hill