1529 search results - page 137 / 306 » On Timing Analysis of Combinational Circuits |
DATE
2000
IEEE
14 years 20 days ago
2000
IEEE
This paper presents a method for redundancy identification (RID) using multi-node logic implications. The algorithm discovers a large number of direct and indirect implications b...
INFOCOM
1992
IEEE
14 years 10 days ago
1992
IEEE
A new packet switch architecture using two sets of time-division multiplexed buses is proposed. The horizontal buses collect packets from the input links, while the vertical buses ...
CAV
2004
Springer
14 years 11 hour ago
2004
Springer
Abstract. CirCUs is a satisfiability solver that works on a combination of AndInverter-Graph, CNF clauses, and BDDs. It has been designed to work well with bounded model checking. ...
RTSS
2003
IEEE
14 years 1 months ago
2003
IEEE
Data caches are essential in modern processors, bridging the widening gap between main memory and processor speeds. However, they yield very complex performance models, which make...
ISCAS
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper proposes two new methods for optimizing objectives and constraints. The GP approach is very general and hardware resources in finite wordlength implementation of it allo...