Sciweavers

1529 search results - page 140 / 306
» On Timing Analysis of Combinational Circuits
Sort
View
DAC
2005
ACM
14 years 9 months ago
Simulation models for side-channel information leaks
Small, embedded integrated circuits (ICs) such as smart cards are vulnerable to so-called side-channel attacks (SCAs). The attacker can gain information by monitoring the power co...
Kris Tiri, Ingrid Verbauwhede
STOC
2010
ACM
216views Algorithms» more  STOC 2010»
14 years 5 months ago
BQP and the Polynomial Hierarchy
The relationship between BQP and PH has been an open problem since the earliest days of quantum computing. We present evidence that quantum computers can solve problems outside th...
Scott Aaronson
VTS
2006
IEEE
133views Hardware» more  VTS 2006»
14 years 2 months ago
PEAKASO: Peak-Temperature Aware Scan-Vector Optimization
— In this paper, an algorithm for scan vector ordering, PEAKASO, is proposed to minimize the peak temperature during scan testing. Given a circuit with scan and the scan vectors,...
Minsik Cho, David Z. Pan
SLIP
2004
ACM
14 years 1 months ago
Interconnect-power dissipation in a microprocessor
Interconnect power is dynamic power dissipation due to switching of interconnection capacitances. This paper describes the characterization of interconnect power in a state-of-the...
Nir Magen, Avinoam Kolodny, Uri C. Weiser, Nachum ...
AICCSA
2008
IEEE
209views Hardware» more  AICCSA 2008»
13 years 10 months ago
Transistor-level based defect tolerance for reliable nanoelectronics
Nanodevices based circuit design will be based on the acceptance that a high percentage of devices in the design will be defective. In this work, we investigate a defect tolerant ...
Aiman H. El-Maleh, Bashir M. Al-Hashimi, Aissa Mel...