1529 search results - page 146 / 306 » On Timing Analysis of Combinational Circuits |
ASPDAC
2011
ACM
12 years 12 months ago
2011
ACM
Abstract— Three-dimensional (3D) integration and Networkon-Chip (NoC) are both proposed to tackle the on-chip interconnect scaling problems, and extensive research efforts have b...
ECMDAFA
2009
Springer
14 years 2 months ago
2009
Springer
The need for a design language that is rigorous but accessible and intuitive is often at odds with the formal and mathematical nature of languages used for analysis. UML and Petri ...
ICCAD
2001
IEEE
14 years 5 months ago
2001
IEEE
Methods based on Boolean satisfiability (SAT) typically use a Conjunctive Normal Form (CNF) representation of the Boolean formula, and exploit the structure of the given problem ...
FPGA
2009
ACM
14 years 3 months ago
2009
ACM
Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates above 100MHz. This combined with FPGA’s lo...
JCO
2011
13 years 3 months ago
2011
Discrete gate sizing is a critical optimization in VLSI circuit design. Given a set of available gate sizes, discrete gate sizing problem asks to assign a size to each gate such th...